In device fabrication, insulating, semiconducting, and conducting layers are formed on a substrate. The layers are patterned to create features and spaces. The minimum dimension or feature size (F) of the features and spaces depends on the resolution capability of the lithographic systems. The features and spaces are patterned so as to form devices, such as transistors, capacitors, and resistors. These devices are then interconnected to achieve a desired electrical function, creating an integrated circuit (IC).
One technique for interconnecting the devices includes depositing a layer of metallic or conductive material, such as aluminum (Al), tungsten (W), or copper (Cu), on a substrate comprising devices and patterning it to form conductors or “lines” that interconnect the devices as desired. Conventional lithographic and etch techniques are used to pattern the conductive layer. Such techniques, for example, deposit a layer of resist and selectively expose the resist with an exposure source and a mask. Depending on whether a positive or negative resist is used, either the exposed or unexposed portions of the resist layer are removed during development. The portions of the underlying metal layer unprotected by the resist are removed, creating the desired metal interconnections lines. Such techniques for forming lines or conductors are referred to as RIE techniques.
An important aspect of forming metal lines is their reliability; that is, the line's time to failure for a given amperage per unit area. Considerable efforts have been made to improve the reliability of conductive lines. Conventionally, it is known that depositing the conductive material such that it has a uniform (111) grain orientation improves the film's reliability. See for example, L. M. Ting and Q-Z. Hong, “Electromigration Characterization for Multilevel Metallizations using Textured AlCu”, Materials Research Society Symposium Proceedings, Vol 428, pp. 75-80 (1996), D. B. Knorr and K. P. Rodbell, “The Role of Texture in the Electromigration Behavior of Pure Aluminum Lines”, J. Appl. Phys. Vol. 79, pp.2409-2417 (1996), C. Ryu, A. L. Loke, T. Nogami and S. S. Wong, “Effect of Texture on the Electromigration of CVD Copper”, IEEE International Reliability Physics Symposium 97CH35983, pp.201-205 (1997).
In advanced IC designs, damascene or dual damascene techniques have been used to form sub-micron conductive lines. The damascene technique includes, for example, first etching submicron trenches in a dielectric material, such as SiO2. Subsequently, the trenches are filled with a conductive material. Typically, Al, Cu, or W is used to fill the trenches. The excess conductive material is removed from the surface above the insulator by chemical-mechanical polishing (CMP). In the dual damascene approach, both trenches and vias are etched in the dielectric material. The vias and trenches are then filled with a conductive material and planarized with CMP, producing a planar surface with conductive lines and vias embedded in the dielectric material.
It has, however, been discovered that as dimensions decrease, increased failures have been found with conventional damascene lines formed with textured materials.
From the above discussion, it is desirable to provide interconnects formed from damascene structures that have improved reliability.